mmmm BRAINS

Now that I have the TinyBX mounted and connected the time has come to get some gateware going. After some research I settled on nMigen. It is constant development and m-labs is working hard to get it running. There is a repository of my code as I develop it.

Boneless CPU

The basis for STEVE’s brain is going to be a Boneless cpu. My current battle is getting a serial port attached to a running CPU so updating and loading software does not require a recompile of the gateware.

Gizmos

Modularity is always an important part of software development. With nMigen giving you access to pythonic encapsulation there are some interesting forms that can be made with gateware. See here , this construct makes it possible to attach gateware into the CPU and map into the memory space with minimal effort.

I have moved my experimental code into a new home on github gizmotron. This will attempt to be a generic Boneless-CPU framework that I can use for STEVE going forwards.

My primary target is the tinyfpga-bx , however with the nmigen-boards system , porting this to a new fpga should be straight forward.

The idea of a gizmo is that you can take an gizmo class extend it bind it directly to the Boneless-CPU external IO. An example to bind all the userleds to a single register is shown below.

import itertools

from nmigen.build import Resource, Subsignal, Pins
from nmigen.build import ResourceError
from .gizmo import Gizmo, IO, BIT

from nmigen import *


class UserLeds(Gizmo):
    def build(self):
        leds = []
        for n in itertools.count():
            try:
                l = self.platform.request("user_led", n)
                print(l)
                leds.append(l)
            except ResourceError:
                break

        leds_cat = Cat(led.o for led in leds)
        o = IO(sig_out=leds_cat, name="user_leds")
        for i, j in enumerate(leds):
            o.add_bit(BIT("led_" + str(i), i))
        self.add_reg(o)

It is also possible to include and Elaboratable into a gizmo

from .gizmo import Gizmo, IO
from nmigen import *


class counter(Elaboratable):
    def __init__(self):
        self.counter = Signal(16)

    def elaborate(self, platform):
        m = Module()
        m.d.sync += self.counter.eq(self.counter + 1)
        return m


class Counter(Gizmo):
    def build(self):
        c = counter()
        self.add_device(c)
        s = IO(sig_in=c.counter, name="counter")
        self.add_reg(s)

This counter is now attached to the cpu , how this is accessed is still in development , but I think that this provides a simple and modular way to add gateware to the boneless cpu.

Investigations continue …